Computer systems once commonly comprised a two-piece chipset architecture consisting of a first chip referred to as a “northbridge” and a second chip referred to as the “southbridge.” In these architectures, the northbridge typically interfaces directly with a central processing unit (CPU) via a front-side bus (FSB) and integrates one or more high-speed components such as memory and graphics controllers. In contrast, the southbridge typically is responsible for integrating slower system components including, for example, various types of input/output (I/O) devices.
However, over time, a bottleneck emerged in such architectures due to the limited bandwidth of the FSB connection between the northbridge and CPU and to the increasing performance requirements of high-speed components integrated with the CPU via the FSB. To help alleviate this bottleneck, modern chipset architectures increasingly integrate many of the high-speed functions once associated with a northbridge into the CPU chip itself to achieve lower data transmission latencies among other benefits. Many of the slower components previously supported by a southbridge typically are still supported by a separate I/O chip in these modern architectures.